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FEATURES Fault and Overvoltage Protection up to 40 V Signal Paths Open Circuit with Power Off Signal Path Resistance of RON with Power On 44 V Supply Maximum Ratings Low On Resistance ADG466/ADG467 60 typ 1 nA Max Path Current Leakage @ +25 C Low R ON Match (5 max) Low Power Dissipation 0.8 W typ Latch-Up Proof Construction APPLICATIONS ATE Equipment Sensitive Measurement Equipment Hot-Insertion Rack Systems
VDD VSS VD1 VD2 VD3 VS1 VS2 VS3
Triple and Octal Channel Protectors ADG466/ADG467
FUNCTIONAL BLOCK DIAGRAMS
VDD VSS VD1 VD2 VD3 VS1 VS2 VS3
ADG466
VIN
VIN
VD8
VS8
VOUT VOUT
ADG467
VDD
VDD
GENERAL DESCRIPTION
The ADG466 and ADG467 are triple and octal channel protectors, respectively. The channel protector is placed in series with the signal path. The channel protector will protect sensitive components from voltage transience in the signal path whether the power supplies are present or not. Because the channel protection works whether the supplies are present or not, the channel protectors are ideal for use in applications where correct power sequencing can't always be guaranteed (e.g., hotinsertion rack systems) to protect analog inputs. This is discussed further, and some example circuits are given in the Applications section of this data sheet. Each channel protector has an independent operation and consists of an n-channel MOSFET, a p-channel MOSFET and an n-channel MOSFET, connected in series. The channel protector behaves just like a series resistor during normal operation, i.e., (VSS + 2 V) < VIN < (VDD - 1.5 V). When a channel's analog input exceeds the power supplies (including VDD and VSS = 0 V), one of the MOSFETs will switch off, clamping the output to either VSS + 2 V or VDD - 1.5 V. Circuitry and signal source protection is provided in the event of an overvoltage or power loss. The channel protectors can withstand overvoltage inputs from -40 V to +40 V. See the Circuit Information section of this data sheet. The ADG466 and ADG467 can operate off both bipolar and unipolar supplies. The channels are normally on when power is connected and open circuit when power is disconnected. With power supplies of 15 V, the on-resistance of the ADG466 and
OUTPUT CLAMPED @ VDD - 1.5V
ADG467 is 60 typ with a leakage current of 1 nA max. When power is disconnected, the input leakage current is approximately 5 nA typ. The ADG466 is available in 8-lead DIP, SOIC and SOIC packages. The ADG467 is available in an 18-lead SOIC package and a 20-lead SSOP package.
PRODUCT HIGHLIGHTS
1. Fault Protection. The ADG466 and ADG467 can withstand continuous voltage inputs from -40 V to +40 V. When a fault occurs due to the power supplies being turned off or due to an overvoltage being applied to the ADG466 and ADG467, the output is clamped. When power is turned off, current is limited to the microampere level. 2. Low Power Dissipation. 3. Low RON. ADG466/ADG467 60 typ. 4. Trench Isolation Latch-Up Proof Construction. A dielectric trench separates the p- and n-channel MOSFETs thereby preventing latch-up.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADG466/ADG467-SPECIFICATIONS
Dual Supply1 (V
Parameter FAULT PROTECTED CHANNEL Fault-Free Analog Signal Range2 RON RON RON Match LEAKAGE CURRENTS Channel Output Leakage, IS(ON) (without Fault Condition) Channel Input Leakage, ID(ON) (with Fault Condition) Channel Input Leakage, ID(OFF) (with Power Off and Fault) Channel Input Leakage, ID(OFF) (with Power Off and Output S/C) POWER REQUIREMENTS IDD ISS VDD/VSS 60 3 4
DD
= +15 V, VSS = -15 V, GND = 0 V, unless otherwise noted)
ADG466 +25 C B1 VSS + 1.2 VDD - 0.8 75 80 4 6 ADG467 +25 C B1 VSS + 1.2 VDD - 0.8 80 95 6 6 Units V min V max typ max max max Test Conditions/Comments Output Open Circuit -10 V VS +10 V, IS = 1 mA -5 V VS +5 V VS = 10 V, IS = 1 mA VS = VD = 10 V nA typ nA max nA typ nA max nA typ nA max A typ A max A typ A max A typ A max V min V max VS = 25 V VD = Open Circuit VDD = 0 V, VSS = 0 V VS = 35 V, VD = Open Circuit VDD = 0 V, VSS = 0 V VS = 35 V, VD = 0 V
62
5
0.1 1 0.2 2 0.5 1 0.005 0.015 0.05 0.5 0.05 0.5 0 20
1 5 0.4 5 2 5 0.1 0.5
0.04 1 0.2 2 0.5 2 0.006 0.015 0.05 0.5 0.05 0.5 0 20
0.2 5 0.4 5 2 10 0.16 0.5
8 8 0 20
8 8 0 20
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. A
ADG466/ADG467
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
PIN CONFIGURATIONS 8-Lead DIP, SOIC and SOIC
VD1 1 VD2 2 8 VDD VD1 1 VD2 2 VD3 3 VD4 4 VD5 5
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VS, VD, Analog Input Overvoltage with Power ON2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 20 V to VDD + 20 V VS, VD, Analog Input Overvoltage with Power OFF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-35 V to +35 V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Plastic DIP Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260C SOIC Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C SOIC Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C SSOP Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at S or D will be clamped by the channel protector, see Circuit Information section of the data sheet.
18-Lead SOIC
18 VDD 17 VS1 16 VS2
ADG466
7 VS1
TOP VIEW VD3 3 (Not to Scale) 6 VS2 VSS 4 5 VS3
ADG467
15 VS3
TOP VIEW 14 VS4 (Not to Scale) VD6 6 13 VS5 VD7 7 VD8 8 VSS 9 12 VS6 11 VS7 10 VS8
20-Lead SSOP
VD1 1 VD2 2 VD3 3 VD4 4 VD5 5 VD6 6 20 NC 19 VDD 18 VS1 17 VS2
ADG467
16 VS3
TOP VIEW 15 VS4 (Not to Scale) VD7 7 14 VS5 VD8 8 VSS 9 NC 10 13 VS6 12 VS7 11 VS8
NC = NO CONNECT
ORDERING GUIDE
Model ADG466BN ADG466BR ADG466BRM ADG467BR ADG467BRS
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead Plastic DIP 8-Lead Small Outline Package 8-Lead Micro Small Outline Package 18-Lead Small Outline Package 20-Lead Shrink Small Outline Package
Package Options N-8 SO-8 RM-8 R-18 RS-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG466/ADG467 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADG466/ADG467-Typical Performance Characteristics
80 75 70 65 60 RON - 55 50 45 0V 40 35 30 -10 -5 16.5V 0 VD - Volts 5 10 -5V VDD, VSS = 15V VDD, VSS = 10V VDD, VSS = 13.5V 5V CHANNEL PROTECTOR OUTPUT VDD, VSS = 5V 15V 10V
ADG466
POSITIVE OVERVOLTAGE ON INPUT RLOAD = 100k CLOAD = 100pF VDD = +10V VSS = -10V
-5V TO +15V STEP INPUT
Ch1
5.00V
Ch2
5.00V
M50.0ns
Ch1
500mV
Figure 1. On Resistance as a Function of VDD and VD (Input Voltage)
Figure 4. Positive Overvoltage Transience Response
70 65 60 0V 55 50 RON - 85 C 45 40 35 -40 C 30 25 -10 -5 0 VD - Volts 5 10 5V TO -15V STEP INPUT 25 C -10V -15V 125 C -5V VDD = +15V VSS = -15V 5V NEGATIVE OVERVOLTAGE ON INPUT RLOAD = 100k CLOAD = 100pF VDD = +10V VSS = -10V CHANNEL PROTECTOR OUTPUT
Ch1
5.00V
Ch2
5.00V
M50.0ns
Ch1
500mV
Figure 2. On Resistance as a Function of Temperature and VD (Input Voltage)
Figure 5. Negative Overvoltage Transience Response
105
ADG467
10V TO +10 V INPUT RLOAD =100k VDD=+5V VSS=-5V
95 5V 1 20V
85
RON -
75 VCLAMP=4.5V 65 15V 13.5V 10V 2 55 VCLAMP=4V 45 -10 -5 0 VD - Volts 5 16.5V 10 Ch1 5.00V Ch2 5.00V M100 s Ch1 500mV OUTPUT
Figure 3. On Resistance as a Function of VDD and VD (Input Voltage)
Figure 6. Overvoltage Ramp
-4-
REV. A
ADG466/ADG467
-10 -12 -14 OFF ISOLATION - dB -16 GAIN - dB -18 -20 -22 -24 -26 -28 -30 1M FREQUENCY - Hz 10M 30M 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10k 100k 1M FREQUENCY - Hz 10M 40M
Figure 7. Frequency Response (Magnitude) of the ADG467, VDD /VSS = 15 V and Input Signal Level of 100 mV
Figure 10. Off Isolation of the ADG467, VDD/V SS = 0 V and Input Signal Level of 100 mV
TEK RUN: 5.00GS/s ET SAMPLE 105.359 82.859 60.359 PHASE - Degrees 37.859 15.359 -7.141 -29.641 -52.161 -76.641 -97.161 100 1k 10k 100k FREQUENCY - Hz 1M 10M 2 12.2ns 1 11.8ns
CH1
2.00V
CH2
2.00V
M 10.0ns
CH1
2.2V
Figure 8. Frequency Response (Phase) of the ADG467, VDD /VSS = 15 V and Input Signal Level of 100 mV
Figure 11. Propagation Delay Through ADG467, VDD/VSS = 15 V, Channel 1 Input and Channel 2 Output
-10 -20 -30 CROSSTALK - dB -40 GAIN - dB 100k 1M FREQUENCY - Hz 10M 40M -50 -60 -70 -80 -90 -100 -110 10k
-10 -14 -18 -22 -26 -30 -36 -38 -42 -46 -50 100k 40M
1M FREQUENCY - Hz
10M
Figure 9. Crosstalk Between Adjacent Channels of the ADG467, VDD/VSS = 15 V and Input Signal Level of 100 mV
Figure 12. Frequency Response (Magnitude) of the ADG466, VDD /VSS = 15 V and Input Signal Level of 100 mV
REV. A
-5-
ADG466/ADG467
105.3 82.8 60.3 OFF ISOLATION - dB PHASE - Degrees 37.8 15.3 -7.1 -29.6 -52.1 -76.6 -92.1 100 1k 10k 100k FREQUENCY - Hz 1M 10M 40M 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10k 100k 1M FREQUENCY - Hz 10M 40M
Figure 13. Frequency Response (Phase) of the ADG466, V DD/ VSS = 15 V and Input Signal Level of 100 mV
Figure 15. Off Isolation of the ADG466, VDD/V SS = 0 V and Input Signal Level of 100 mV
TEK RUN: 2.5GS/s ET SAMPLE 0 -10 -20 CROSSTALK - dB -30 -40 -50 -60 18.0ns -70 -80 -90 -100 10k 100k 1M FREQUENCY - Hz 10M 40M 2 1 22.0ns
CH1
1.00V
CH2
1.00V
M 20.0ns
CH1
760V
Figure 14. Crosstalk Between Adjacent Channels of the ADG466, VDD/VSS = 15 V and Input Signal Level of 100 mV
Figure 16. Propagation Delay Through ADG466, VDD/VSS = 15 V, Channel 1 Input and Channel 2 Output
-6-
REV. A
ADG466/ADG467
CIRCUIT INFORMATION
Figure 17 below shows a simplified schematic of a channel protector circuit. The circuit is made up of four MOS transistors--two NMOS and two PMOS. One of the PMOS devices does not lie directly in the signal path but is used to connect the source of the second PMOS device to its backgate. This has the effect of lowering the threshold voltage and so increasing the input signal range of the channel for normal operation. The source and backgate of the NMOS devices are connected for the same reason. During normal operation the channel protectors have a resistance of 60 typ. The channel protectors are very low power devices, and even under fault conditions the supply current is limited to sub microampere levels. All transistors are dielectrically isolated from each other using a trench isolation method. This makes it impossible to latch up the channel protectors. For an explanation, see Trench Isolation section.
case of a negative overvoltage the threshold voltage is given by VSS - VTP where VTP is the threshold voltage of the PMOS device (2 V typ). If the input voltage exceeds these threshold voltages, the output of the channel protector (no load) is clamped at these threshold voltages. However, the channel protector output will clamp at a voltage that is inside these thresholds if the output is loaded. For example with an output load of 1 k, VDD = 15 V and a positive overvoltage. The output will clamp at VDD - VTN - V = 15 V - 1.5 V - 0.6 V = 12.9 V where V is due to I x R voltage drop across the channels of the MOS devices (see Figure 19). As can be seen from Figure 19, the current during fault condition is determined by the load on the output (i.e., VCLAMP/RL ). However, if the supplies are off, the fault current is limited to the nano-ampere level. Figures 18, 20 and 21 show the operating conditions of the signal path transistors during various fault conditions. Figure 18 shows how the channel protectors operate when a positive overvoltage is applied to the channel protector.
VDD - VTN* (+13.5V)
VSS
PMOS NMOS NMOS
POSITIVE OVERVOLTAGE (+20V)
NMOS
PMOS
NMOS
PMOS VDD VSS VDD
SATURATED
NONSATURATED VSS (-15V)
NONSATURATED VDD (+15V)
VDD (+15V)
*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)
Figure 17. The Channel Protector Circuit
Overvoltage Protection
Figure 18. Positive Overvoltage on the Channel Protector
When a fault condition occurs on the input of a channel protector, the voltage on the input has exceeded some threshold voltage set by the supply rail voltages. The threshold voltages are related to the supply rails as follows. For a positive overvoltage, the threshold voltage is given by VDD - VT where VTN is the threshold voltage of the NMOS transistor (1.5 V typ). In the
The first NMOS transistor goes into a saturated mode of operation as the voltage on its Drain exceeds the Gate voltage (VDD) - the threshold voltage (VTN). This situation is shown in Figure 19. The potential at the source of the NMOS device is equal to VDD - VTN. The other MOS devices are in a nonsaturated mode of operations.
VD (+20V)
VG (VDD =15V)
VS (+13.5V) PMOS
V
NMOS VCLAMP RL
N+ OVERVOLTAGE OPERATION (SATURATED)
N CHANNEL
EFFECTIVE SPACE CHARGE REGION
N+
N+
NONSATURATED OPERATION IOUT
VT = 1.5V
P-
(VG - VT = 13.5V)
Figure 19. Positive Overvoltages Operation of the Channel Protector
REV. A
-7-
ADG466/ADG467
When a negative overvoltage is applied to the channel protector circuit, the PMOS transistor enters a saturated mode of operation as the drain voltage exceeds VSS - VTP. See Figure 20 below. As in the case of the positive overvoltage, the other MOS devices are nonsaturated.
NEGATIVE OVERVOLTAGE (-20V) NEGATIVE OVERVOLTAGE (-20V) NMOS PMOS VSS - VTP* (-13V) NMOS
TRENCH ISOLATION
The MOS devices that make up the channel protector are isolated from each other by an oxide layer (trench) (see Figure 22). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of "latch-up" caused by parasitic junctions between CMOS transistors. Latchup is caused when P-N junctions that are normally reverse biased become forward biased, causing large currents to flow, which can be destructive. CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation, the N and P wells of the CMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up proof circuit.
VG VS VD VS VG VD
SATURATED NONSATURATED VSS (-15V) VDD (+15V) *VTP = PMOS THRESHOLD VOLTAGE (-2V)
NONSATURATED VDD (+15V)
Figure 20. Negative Overvoltage on the Channel Protector
The channel protector is also functional when the supply rails are down (e.g., power failure) or momentarily unconnected (e.g., rack system). This is where the channel protector has an advantage over more conventional protection methods such as diode clamping (see Applications Information). When VDD and VSS equal 0 V, all transistors are off and the current is limited to subnano-ampere levels (see Figure 21).
(0V)
T R E N C H
P+
P-CHANNEL
P+
N-
T R E N C H
N+
N-CHANNEL
N+
P-
T R E N C H
POSITIVE OR NEGATIVE OVERVOLTAGE
NMOS
PMOS
NMOS
BURIED OXIDE LAYER SUBSTRATE (BACKGATE)
OFF VDD (0V)
OFF VSS (0V)
OFF VDD (0V)
Figure 22. Trench Isolation
Figure 21. Channel Protector Supplies Equal to Zero Volts
-8-
REV. A
ADG466/ADG467
APPLICATIONS INFORMATION Overvoltage and Power Supply Sequencing Protection
Again this ensures that signals on the inputs of the CMOS devices never exceed the supplies.
High Voltage Surge Suppression
The ADG466 and ADG467 are ideal for use in applications where input overvoltage protection is required and correct power supply sequencing cannot always be guaranteed. The overvoltage protection ensures that the output voltage of the channel protector will not exceed the threshold voltages set by the supplies (see Circuit Information) when there is an overvoltage on the input. When the input voltage does not exceed these threshold voltages, the channel protector behaves like a series resistor (60 typ). The resistance of the channel protector does vary slightly with operating conditions (see Typical Performance Graphs). The power sequencing protection is afforded by the fact that when the supplies to the channel protector are not connected, the channel protector becomes a high resistance device. Under this condition all transistors in the channel protector are off and the only currents that flow are leakage currents, which are at the A level.
EDGE CONNECTOR +5V -5V VDD VSS
The ADG466 and ADG467 are not intended for use in high voltage applications like surge suppression. The ADG466 and ADG467 have breakdown voltages of VSS - 20 V and VDD + 20 V on the inputs when the power supplies are connected. When the power supplies are disconnected, the breakdown voltages on the input of the channel protector are 35 V. In applications where inputs are likely to be subject to overvoltages exceeding the breakdown voltages quoted for the channel protectors, transient voltage suppressors (TVSs) should be used. These devices are commonly used to protect vulnerable circuits from electric overstress such as that caused by electrostatic discharge, inductive load switching and induced lightning. However, TVSs can have a substantial standby (leakage) current (300 A typ) at the reverse standoff voltage. The reverse standoff voltage of a TVS is the normal peak operating voltage of the circuit. Also TVS offer no protection against latch-up of sensitive CMOS devices when the power supplies are off. The best solution is to use a channel protector in conjunction with a TVS to provide the best leakage current specification and circuit protection.
VDD = +5V VSS = -5V
ADC
ANALOG IN -2.5V TO +2.5V LOGIC
ADC
ADG466
CONTROL LOGIC TVSs BREAKDOWN VOLTAGE = 20V
LOGIC
ADG466
GND
Figure 24. High Voltage Protection Figure 23. Overvoltage and Power Supply Sequencing Protection
Figure 23 shows a typical application that requires overvoltage and power supply sequencing protection. The application shows a Hot-Insertion rack system. This involves plugging a circuit board or module into a live rack via an edge connector. In this type of application it is not possible to guarantee correct power supply sequencing. Correct power supply sequencing means that the power supplies should be connected before any external signals. Incorrect power sequencing can cause a CMOS device to "latch up." This is true of most CMOS devices regardless of the functionality. RC networks are used on the supplies of the channel protector (Figure 23) to ensure that the rest of the circuitry is powered up before the channel protectors. In this way, the outputs of the channel protectors are clamped well below VDD and VSS until the capacitors are charged. The diodes ensure that the supplies on the channel protector never exceed the supply rails of the board when it is being disconnected.
Figure 24 shows an input protection scheme that uses both a TVS and channel protector. The TVS is selected with a reverse standoff voltage that is much greater than operating voltage of the circuit (TVSs with higher breakdown voltages tend to have better standby leakage current specifications) but is inside the breakdown voltage of the channel protector. This circuit protects the circuitry whether the power supplies are present or not.
REV. A
-9-
ADG466/ADG467
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
8-Lead Small Outline IC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.280 (7.11) 0.240 (6.10)
1 4
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC
0.015 (0.381) 0.008 (0.204)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
18-Lead Small Outline IC (R-18)
0.4625 (11.75) 0.4469 (11.35)
18 10
20-Lead Shrink Small Outline Package (RS-20)
0.295 (7.50) 0.271 (6.90)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
20
11
1
9
0.311 (7.9) 0.301 (7.64)
1
10
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) x 45 0.0098 (0.25)
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.78) 0.066 (1.67)
0.0118 (0.30) 0.0040 (0.10)
8 0.0500 0.0192 (0.49) 0 (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC SEATING 0.009 (0.229) PLANE 0.005 (0.127)
0.212 (5.38) 0.205 (5.21)
8 0
0.037 (0.94) 0.022 (0.559)
8-Lead Micro Small Outline IC (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33 27 0.028 (0.71) 0.016 (0.41) 0.120 (3.05) 0.112 (2.84)
-10-
REV. A
PRINTED IN U.S.A.
C2207a-0-5/98

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